1. Field of the Invention
The present invention is related to the detection of voltage in integrated circuits. More specifically, the present invention is related to the detection of on-chip generated voltage levels and regulation of those on-chip-generated voltages.
2. Relevant Background
In a modern integrated circuit, there are many voltage levels required for proper operation. However, to simplify the input/output connection system of the integrated circuit (i.e., minimize the number of pins), customers have demanded very simple power supply requirements with one ground input and one power supply input pin. Integrated circuit manufacturers have responded by providing integrated circuits that generate on-chip voltages to satisfy performance requirements. These on-chip voltage generators use devices such as current pumps to boost the voltage or lower the voltage to the appropriate level. These voltage generators must be carefully regulated to provide the appropriate voltage on the integrated circuit.
FIG. 1 is a schematic diagram of a prior art voltage regulator for determining the voltage level of a voltage boosted above the power supply voltage, commonly referred to as V.sub.pp. V.sub.pp is connected to the drain of P-channel transistor 10. The gate of P-channel transistor 10 is tied to the source of P-channel transistor 10. The source of P-channel transistor 10 is connected to the drain of P-channel transistor 12. The gate of transistor 12 is connected to a reference potential V.sub.Ref. The source of transistor 12 is connected to the drain of P-channel transistor 14, which has its gate connected to a ground potential and its source connected to a ground potential. In this configuration, the voltage at node 16 is pulled to near ground unless the voltage on the source of transistor 12 is pulled to higher than one V.sub.t above V.sub.Ref, in which case the voltage on node 16 will be pulled high.
A reference potential V.sub.Ref2 is connected to the gate of N-type transistor 18. The output of node 16 is connected to N-type transistor 20. These transistors are connected in the format of a differential amplifier, which is switched on and off by voltages applied to the gates of transistors 22 and 24. P-type transistors 26 and 28 provide pull-up potential for the differential amplifier. The output of the differential amplifier is provided on the gates of P-channel transistor 30 and N-channel transistor 31. Transistors 30 and 31 provide a complimentary inverter, which is pulled up by P-type transistors 34 and 36 and pulled down by N-channel transistors 38 and 40. Transistors 22, 38, and 34 are narrow, low-current transistors. Transistors 24, 36, and 40 are wide, high-current driving transistors. On the pull-up side of the inverter including transistors 30 and 31, transistor 36 provides a strong pull-up and transistor 34 provides a weak pull-up. When the output of the inverter pair transistor 30 and 31 is high, it indicates that the voltage on the gate of transistor 20 is a lower voltage than V.sub.Ref2 provided on the gate of transistor 18. This indicates that pumping is required to bring V.sub.pp to its proper voltage level.
The high voltage thus provided on the input of inverter 42 is inverted to a low output, which causes NOR gate 44 to provide a high output which is inverted by inverter 46 to provide a low output. This low output causes transistor 36 to remain on providing a high pull-up current source. The output of inverter 46 is inverted by inverter 48 to provide a high voltage, which causes transistor 34 to be off. Because transistor 36 is capable of providing higher drive current, this system provides a bias in the circuit to provide an "on" signal and thus to provide pumping for the generators generating V.sub.pp. In a similar manner, the Enable signal provided to the gates of transistors 24 and 40 caused transistors 24 and 40 to provide stronger pull-down and thus faster operation when the enable signal is provided.
The input V.sub.pump provides an override to the circuit under various conditions indicated by high utilization of the integrated circuit. When V.sub.pump is high the output of inverter 50 is low which causes the output of NOR gate 44 to be high regardless of the input provided by inverter 42.
The threshold voltages of transistors 10 and 12 determine the triggering point of the voltage detector of FIG. 1. Threshold voltage varies with process variations in the fabrication of an integrated circuit containing the circuit of FIG. 1 and with the temperature of operation of the circuit. Thus the triggering point cannot be precisely set. Therefore, the prior art circuit of FIG. 1 does not have the stability in the face of process variations and temperature variations necessary for today's high density, and thus highly sensitive, integrated circuitry.
FIG. 2 is a schematic diagram of another prior art V.sub.pp detector. V.sub.pp is provided to the source of P-channel transistor 110. The gate of transistor 110 is connected to a reference voltage V.sub.Ref. The drain of transistor 110 is connected to the source of P-channel transistor 1 12. The gate of transistor 1 12 is connected to a detection enable signal. Detection is enabled by the Enable signal going low, thus turning on transistor 112. Also, the Enable signal is provided to the gate of N-channel transistor 114, which is thus turned off. When the Enable signal is high, thus indicating that the detection is disabled, transistor 114 is on and the gate of transistor 116 is clamped to ground.
When the enable signal is low, transistor 114 is off and the voltage level on node 115 is determined by the voltage level of V.sub.pp. As V.sub.pp rises above one V.sub.t above V.sub.Ref, transistor 110 is turned on and node 115 is pulled high. A high voltage on node 115 causes transistor 116 to turn on. Transistor 116 is placed in series with pull-up transistor 120 which is a P-type transistor having its gate connected to ground and is source connected to Power supply 2. Transistor 122 is a pull-down transistor having its source connected to ground and its gate connected to Power supply 2. These two transistors are designed to have relatively high resistance and thus provide current pull-up and pull-down sources. Thus, the voltage at node 124 is determined solely by the state of transistor 116. When transistor 116 is on, the voltage point at node 124 is pulled low thus causing inverter 126 to have a high output and inverter 128 to have a low output. The voltage changes are damped by transistor 130, which is connected with its gate to the input of inverter 126 and both its source and drain to ground. This provides a capacitive function, which provides a time delay for the input at node 124. Inverters 126 and 128 feed step-down latch 132 which provides an output to the input of inverter 134 which is non-inverted from the input of inverter 126. The output of inverter 134 is inverted by inverter 136, thus providing a fully latched and buffered output of the circuit.
The voltage level detected in the circuit of FIG. 2 is highly dependent upon the threshold voltage of transistor 110. This characteristic is highly dependent upon process variations and temperature variations. Thus, the detector of FIG. 2 provides an unacceptable process variation for modern highly integrated circuits.
FIG. 3 is a prior art diagram of a V.sub.bb or substrate voltage detector. It is common in the industry to provide a substrate voltage lower than the lowest supplied voltage. Providing a high Enable signal, which turns off transistors 210 and 212, enables the detector of FIG. 3. The gate of transistor 218 is connected to ground. The gate of N-channel transistor 222 is also connected to ground. Transistors 224 and 226 have their gates connected to their drains, thus providing a two V.sub.t voltage drop from V.sub.bb to the source of transistor 222. When the source of transistor 222 is pulled one V.sub.t below ground the desired level by V.sub.bb going below the desired level, transistor 222 is on, and the gate of transistor of 228 is pulled to ground. Thus, transistor 228 is off. This low level also passes through transistor 218 to the gate of transistor 230, which is a P-channel transistor. Thus, P-channel transistor 230 is on.
When V.sub.bb rises to the level that transistor 228 is on, the input to inverter 250 is pulled to low and thus the output of inverter 250 is high. Transistors 230, 248, 228 and 246 form a NAND gate. A NAND gate with it's output NOTed is the functional equivalent of an OR gate. Thus, this NAND gate coupled with inverter 250 provide an OR gate. The Enable bar signal is low if the circuit of FIG. 3 is in operation, thus the output of inverter 211 is high. This combined with the high output of inverter 250 causes NAND gate 252 to provide a low output, signaling that the V.sub.bb pumps should pump to lower the V.sub.bb voltage level.
To provide a hysteresis effect, the circuit of FIG. 3 includes a double detection scheme. The second detector is provided when the enable bar signal turns on transistor 232. Transistor 212 has its gate connected to the source of transistor 210, thus providing the voltage drops from V.sub.dd established by transistors 210, 214, and 216. V.sub.bb is connected to the source of N-channel transistor 234 whose gate and drain are connected to the source of N-channel transistor 236. Thus, the drain of transistor 236 is two threshold voltage drops above V.sub.bb. Transistors 236 and 234 are doped to provide higher threshold voltages than those of transistors 224 and 226. When the level of V.sub.bb goes below 3 threshold voltage drops, the gate of transistor 238 which is tied to ground is 1 threshold voltage higher than the drain of transistor 238. When V.sub.bb drops below this voltage (which is lower than the turn on point for transistor 222 because of the higher threshold voltages of transistors 236 and 234), transistor 240 is turned on and transistor 242 is turned off. Transistors 240, 242, 254 and 256 form a NOR gate with one input being the output of inverter 250 and the other being the level of V.sub.bb as determined by transistors 234, 236 and 238.
Because the output of inverter 250 is triggered to a high output by a higher (less negative) voltage than the voltage at which transistor 240 is turned off and transistor 242 turned on (because of the larger threshold voltages of transistors 234 and 236), transistor 242 will always be on when the output of inverter 250 goes high. Thus the input of inverter 244 is pulled low causing the voltage applied to the gates of transistors 246 and 248 to go high. This provides a latching effect because this causes inverter 250 to provide a high output regardless of the state of transistors 228 and 230. Once this latching effect has occurred, the level detection provided by transistors 234, 236 and 238 is in control. Only when V.sub.bb goes low enough (negative enough) to cause transistor 238 to turn on will the "latch" change states.
In certain circumstances, the substrate pump must be shut off under all circumstances, regardless of the voltage level detected by the voltage level detectors. In these circumstances Enable bar is brought high causing the V.sub.bb stop output signal provided by NAND gate 252 to be high regardless of the input signals provided by inverter 250.
As can be readily ascertained from the operation of the circuit of FIG. 3, this circuit is highly dependent on the threshold voltages of transistors 222, 224, 226, 236, 234, and 238. These behavioral characteristics are highly dependent upon process variations and thus are not acceptable for the highly sensitive circuitry of today's high density integrated circuits.